China Just Build What TSMC Said Was Impossible
Credibility score: 48/100 — Mixed Credibility. Several questionable claims detected. Watch with healthy skepticism.
BSmeter analyzed "China Just Build What TSMC Said Was Impossible" and rated it 48/100 for credibility (a BS score of 52/100 — mixed credibility), on 2026-06-17. Its weakest claim — "Huawei's Tau scaling uses Einstein's time-space correlation" — scored 25/100 and was flagged as sketchy. 8 claims were checked against the video transcript. Scores are produced by BSmeter's AI analysis of the transcript, not independent human verification.
Of 8 claims analyzed: 2 scored under 40, 5 between 40 and 69, and 1 at 70 or above.
Claims analyzed
Huawei announced 1.4nm chips without EUV lithography by shrinking time instead — Dubious (35/100)
At 0:00
No actual announcement exists — this is just wild speculation dressed up as news 💀
Why this score: No public record of any Huawei 1.4nm announcement. Key issues:
- Current leading nodes sit at 2nm with EUV; skipping that is a massive leap
- 'Shrinking time' is marketing fluff, not a technical process
- No patents, papers, or official statements back this up
Original quote: “[0:00] China just announced a new way to build microchips that will bring them to 1.4 nanometer transistors [0:08] without leading edge lithography. Instead of shrinking transistors, Huawei wants to shrink something else. Time.”
TSMC's A14 node only gets ~6% area gains — Unverifiable (50/100)
At 0:30
Drops a super-specific 6% number with zero source — feels like it came straight from a slide deck we can't see 💀
Why this score: No public data backs the exact 6% figure yet.
- A14 process details are still under NDA
- TSMC roadmaps usually stay vague until closer to production
- Could be accurate insider info or just marketing rounding
Original quote: “Each new generation delivers smaller gains while becoming dramatically more expensive. In fact, with the upcoming A14 transistor generation, TSMC is fighting for roughly a 6% area gains.”
NVIDIA GPU has 340 billion transistors on two chips — Dubious (40/100)
At 2:30
340 billion? NVIDIA's biggest chips are ~80B right now — this number is straight fanfic 🤡
Why this score: No NVIDIA product has 340 billion transistors.
- Blackwell B200 reaches ~208B across two dies; Hopper H100 is ~80B.
- The 340B figure has no matching public roadmap or disclosed die size.
Original quote: “Take a look at this NVIDIA GPU. It's 340 billion transistors spread across two flat pieces of silicon.”
Huawei's Tau scaling uses Einstein's time-space correlation — Sketchy (25/100)
At 4:30
Bro dragged Einstein into chip stacking like he's the new thermal engineer 💀
Why this score: Misuse of relativity.
- Einstein's work describes spacetime at cosmic scales, not RC delays on silicon
- No actual physics paper links general relativity to 3D chip timing
- Pure metaphor dressed as deep theory
Original quote: “And this idea sits at the core of Huawei's Tau scaling strategy. And actually Einstein showed us that time and space are fundamentally correlated.”
Huawei claims 1.5-micron hybrid bonding tech far ahead of AMD/TSMC at 9 microns — Dubious (45/100)
At 8:30
Speaker treats 1.5-micron bonding pitch as proven Huawei capability — but it's still a target, not delivered silicon.
Why this score: No public evidence Huawei has shipped 1.5-micron hybrid bonding. Key issues:
- Current industry leaders (AMD, Intel, TSMC) remain at ~9 microns per multiple 2025 reports
- Huawei presentation frames 1.5 microns as future roadmap goal, not current product
- Achieving that pitch at scale would require major process breakthroughs still unverified outside company slides
Original quote: “Huawei is betting its entire scaling road map on a single number, 1.5 microns, more specifically 1.5 micron hybrid bonding. ... today's state-of-the-art is around 9 micron. AMD's 3GV cache uses bonding pitches around 9 microns. Intel and TSMC are in a similar range, while Huawei is talking about…”
Huawei pushing smaller chip pitches requires entirely new tools and processes — Solid (75/100)
At 10:30
Basic semiconductor reality — shrinking nodes always demands new equipment. Not groundbreaking, just how the industry works.
Why this score: Standard industry pattern.
- Every node shrink (7nm→5nm→3nm) forces new lithography, materials, and assembly methods.
- TSMC, Intel, and Samsung have all documented this exact cycle.
- Huawei faces the same constraints; nothing unique claimed here.
Original quote: “And this is incredibly aggressive. And this is not just the bonding challenge. Every time you push to smaller pitches, you need new manufacturing tools, new processes, and new recipes of assembling and testing these devices.”
AMD stacks memory on processors and HBM uses 12 dies — OK (65/100)
At 12:30
AMD does 3D stacking and HBM does stack high — number 12 feels pulled from thin air though.
Why this score: Mostly right, detail shaky.
- AMD uses 3D V-Cache stacking on CPUs
- HBM stacks multiple dies vertically
- Specific claim of exactly 12 dies lacks confirmation in current tech
Original quote: “AMD stacks memory on top of the processor. HBM stacks 12 memory dies”
Huawei claims logic folding hits 1.4nm-class density by 2031, 238M transistors/mm² now — Dubious (45/100)
At 14:30
Calling stacking '1.4nm class' is marketing sleight of hand — two mature layers don't equal a new node 💀
Why this score: No actual 1.4nm process. Key issues:
- Stacking mature nodes increases density but doesn't create new lithography nodes
- True 1.4nm requires sub-2nm features that current Chinese fabs can't produce
- The 'equivalent' phrasing is industry-standard weasel language
Original quote: “According to Huawei, with logic folding, they could eventually achieve 1.4 nanometer class transistor density by 2031. In 2026, logical folding take it all the way to 238 million transistor per square millimeter in one single step.”
See the full analysis with timestamps →