China Just Build What TSMC Said Was Impossible
Credibility score: 48/100 — Mixed Credibility. Several questionable claims detected. Watch with healthy skepticism.
Claims analyzed
Huawei announced 1.4nm chips without EUV lithography by shrinking time instead — Dubious (35/100)
No actual announcement exists — this is just wild speculation dressed up as news 💀
TSMC's A14 node only gets ~6% area gains — Unverifiable (50/100)
Drops a super-specific 6% number with zero source — feels like it came straight from a slide deck we can't see 💀
NVIDIA GPU has 340 billion transistors on two chips — Dubious (40/100)
340 billion? NVIDIA's biggest chips are ~80B right now — this number is straight fanfic 🤡
Huawei's Tau scaling uses Einstein's time-space correlation — Sketchy (25/100)
Bro dragged Einstein into chip stacking like he's the new thermal engineer 💀
Plug for Plaud Note Pro with 17% off code ANASTASI — Sponsored (50/100)
Straight sponsor read — code ANASTASI for 17% off, link in description. Classic mid-video ad.
Huawei claims 1.5-micron hybrid bonding tech far ahead of AMD/TSMC at 9 microns — Dubious (45/100)
Speaker treats 1.5-micron bonding pitch as proven Huawei capability — but it's still a target, not delivered silicon.
Huawei pushing smaller chip pitches requires entirely new tools and processes — Solid (75/100)
Basic semiconductor reality — shrinking nodes always demands new equipment. Not groundbreaking, just how the industry works.
AMD stacks memory on processors and HBM uses 12 dies — OK (65/100)
AMD does 3D stacking and HBM does stack high — number 12 feels pulled from thin air though.
Huawei claims logic folding hits 1.4nm-class density by 2031, 238M transistors/mm² now — Dubious (45/100)
Calling stacking '1.4nm class' is marketing sleight of hand — two mature layers don't equal a new node 💀
See the full analysis with sources and timestamps →