The Terrifying Reality Of New TSMC's Chips
Credibility score: 75/100 — Mostly Credible. Mixed credibility - some claims are solid, others need verification.
BSmeter analyzed "The Terrifying Reality Of New TSMC's Chips" and rated it 75/100 for credibility (a BS score of 25/100 — mostly credible), on 2026-05-12. Its weakest claim — "TSMC's new chips only 6% improvement" — scored 45/100 and was flagged as dubious. 31 claims were checked against the video transcript. Scores are produced by BSmeter's AI analysis of the transcript, not independent human verification.
Of 31 claims analyzed: 0 scored under 40, 8 between 40 and 69, and 23 at 70 or above.
Claims analyzed
TSMC unveiled 14A and 12A chip tech — Solid (75/100)
At 0:00
👌
Why this score: TSMC roadmap aligns.
- TSMC's official announcements confirm A14 (1.4nm) and A12 (1.2nm) as next-gen nodes post-A2nm, with reveals in 2024-2025 roadmaps.
- 'Biggest chip makers war' is hype but TSMC vs. Intel/Samsung rivalry is real amid 2nm race.
Original quote: “The two biggest chip makers on Earth are heading into a war and it's happening at the absolute edge of physics. TSMC just unveiled their 14 angstrom and 12 angstrom microchip technology.”
Past transistor gens gave 30-50% gains — Solid (80/100)
At 0:14
✅
Why this score: Historical scaling matches.
- Moore's Law and Dennard scaling delivered ~30-50% performance/area gains per node (e.g., 90nm→65nm eras).
- Speaker's engineer cred adds weight; figures align with industry retrospectives.
Original quote: “And to the outside world, this looks like incredible progress. But as a chip design engineer, I can tell you the math is actually terrifying. For decades, every new transistor generation delivered massive gains like 30 to 50%.”
TSMC's new chips only 6% improvement — Dubious (45/100)
At 0:27
6%? That's a suspiciously round number with zero math shown 🚩
Why this score: Claim oversimplifies without evidence.
- No public TSMC data specifies '6%' for A14/A12 vs. prior; scaling now focuses on PPA (power/performance/area) tradeoffs, not single %.
- 'Terrifying math' sounds engineered for drama—real gains are multidimensional (e.g., N2 claims 15% speed/25-30% power over N3). Needs source.
Original quote: “And now TSMC is fighting for just 6% improvement. That's what's”
Moore's Law now just 6% gains vs past 30-50%, AI needs 100x compute — Solid (75/100)
At 0:30
👌
Why this score: Moore's Law slowdown accurate.
- Historical doubling (~100% every 2yrs) slowed to ~3-4yrs; 6% transistor density gain matches TSMC A13 specs.
- AI compute demand exploding with $725B capex in 2026, though exact '100x' is directional.
Original quote: “massive gains like 30 to 50%. And now TSMC is fighting for just 6% improvement. That's what's left of Moore's law. While AI demand requires 100 times more compute. ... For 50 years, the rule was simple. Make the transistor smaller and everything gets twice faster.”
Scaling breaking at single-digit nm due to electron tunneling — Verified (90/100)
At 1:43
✅
Why this score: Quantum tunneling at <10nm is established physics.
- Electrons tunnel through thin insulators, causing leakage/reliability issues in modern nodes.
- Industry consensus: key limit slowing Moore's Law toward 2030-2040 plateau.
Original quote: “We went from room sized mainframes to laptops to AI. And now we are back to computers that fill entire buildings. We call them data centers. But now that scaling rule is breaking as we push silicon to the limit. ... electrons stop behaving. They tunnel through barriers that are never supposed to…”
Transistor reinvented: FinFETs ~10yrs ago, now GAA — Solid (85/100)
At 2:11
✅
Why this score: Transistor evolution timeline spot-on.
- FinFETs introduced ~2011 (Intel), decade ago from 2021+.
- GAA/nanosheets now in TSMC N2 (2025), Intel 18A (2025), A16.
Original quote: “So the industry had to reinvent the transistor. The last time it happened was a decade ago with FinFETs and now it's happening again and this time it's gate-all-around (GAA).”
TSMC introduced A14/A13/A12 nodes, 6% transistor gain — Solid (80/100)
At 2:18
👌
Why this score: TSMC angstrom nodes real, timelines align.
- A14 for 2028, A13 (shrink) 2029 w/ 6% density gain; A16 GAA unveil June 2026.
- 2nm vol prod Q4 2025; 'just entered' fits 2026 context.
Original quote: “We've just entered the 2 nanometers era. But TSMC and Intel are already moving beyond it. TSMC just introduced A14, A13 and A12 process nodes where A stands for angstrom which is 1/10 of a nanometer. ... even at that scale you get about 6% more transistors in the same area just 6%”
FinFET controls channel from 3 sides, now switched to nanosheets GAA — Verified (95/100)
At 2:32
✅👌
Why this score: Accurate description of FinFET to GAA transition.
- FinFET gates control from 3 sides, reaching limits below 3nm due to leakage.
- GAA/nanosheet FETs wrap gate fully around channel for better control, now in TSMC's N2 (2nm) production per 2026 updates.
Original quote: “today's transistor FinFET, the gate controls the channel from three sides. That used to be enough. Now it isn't. That's where a control breaks. So the structure had to change. Instead of one fin, you split the channel into nanosheets and wrap the gate around all of them.”
TSMC shifting to mega chips instead of shrinking transistors — Solid (85/100)
At 3:10
Spot on shift to advanced packaging 👌
Why this score: TSMC's mega-chip strategy aligns with industry trend.
- Moving beyond transistor scaling slowdown (Moore's Law ~3-4 years now) to chiplet-based mega chips.
- Combines compute dies, memory via advanced packaging to overcome single-die limits.
Original quote: “This is where the two biggest chip makers on earth split completely. One answer is radical. You stop building microchips and start building mega chips. This is TSMC's approach. You don't scale by making one chip much smaller anymore. You scale by building something much bigger.”
EUV reticle limit is 26x33mm max chip size — Verified (98/100)
At 3:45
✅
Why this score: Standard EUV reticle limit confirmed.
- Reticle field size is precisely ~26x33mm in ASML EUV tools.
- Prevents printing larger single chips without stitching/multi-exposure.
Original quote: “Inside an EUV machine, light projects a pattern onto silicon, but it can't print an infinite area. It can only expose one fixed rectangle at a time. Think of it like a stencil about 26 by 33 mm in size. That's your maximum chip size. That limit is called the reticle.”
TSMC building 14-40 reticle mega chips with chiplets — OK (65/100)
At 4:14
Direction right, exact reticle #'s fuzzy ⚠️
Why this score: Concept solid but specifics mid.
- TSMC uses chiplet stitching for large packages like CoWoS to beat reticle limits.
- 14-40 reticle sizes match multi-reticle mega-package trends (e.g., >1000mm²), but no exact public TSMC quote for '40 reticle'—plausible for future AI/HPC.
Original quote: “They are taking many chips, compute dies, memory, interconnect layers and stitching them together inside one massive mega chip. Now TSMC is moving towards systems the size of 14 reticles and eventually much larger toward 40 reticle mega chips.”
Shrinking transistors gives only 6% gains, advanced packaging gives orders of magnitude more — Solid (80/100)
At 4:30
👌
Why this score: Accurate on scaling limits vs packaging.
- Transistor shrinks (Dennard scaling end) yield ~6% perf gains; advanced packaging (2.5D/3D, chiplets) delivers 10x+ via density/bandwidth.
- Web context confirms packaging as primary driver now.
Original quote: “if shrinking transistor gives you just 6% but rebuilding the system gives you orders of magnitude more the choice is obvious”
TSMC saying no to High-NA EUV for now, costs $400M per tool — Verified (95/100)
At 5:01
✅💯
Why this score: Spot-on TSMC strategy and cost.
- TSMC not rushing High-NA EUV before 2029, using for R&D only; cost $350-400M confirmed.
- Matches web context on TSMC's Kevin Zhang statements.
Original quote: “They are saying no to High-NA EUV machines at least for now... High-NA EUV is ASML's next generation lithography machine. It costs roughly $400 million per tool”
High-NA EUV slows throughput, adds risk, more expensive wafers; TSMC skips for now — Solid (85/100)
At 5:46
👌
Why this score: TSMC's risk assessment aligns with reality.
- High-NA lowers throughput, raises costs/risks; TSMC prioritizes scale/reliability over bleeding-edge.
- Web confirms TSMC extracting value from existing EUV instead.
Original quote: “High-NA pushes resolution forward, but it slows throughput. It adds risk and it makes every wafer more expensive. So TSMC looked at this and makes a very clean call. This doesn't worth the risk. not now”
TSMC using multi-patterning on existing EUV instead — Solid (80/100)
At 6:16
✅
Why this score: Confirmed TSMC approach.
- TSMC relies on multi-patterning existing EUV for sub-2nm equivalents, avoiding High-NA risks.
- Web context supports continuation of low-NA EUV optimization.
Original quote: “and instead they decide to push the existing EUV further using multi-patterning.”
TSMC optimizes for yield, cost, scale over aggressive innovation — Verified (90/100)
At 6:30
👌✅
Why this score: Spot-on description of TSMC's strategy.
- TSMC leads via operational excellence in advanced nodes (N3, N2), prioritizing yields and scale per industry reports.
- Web context confirms focus on shippable tech, contrasting Intel's risks.
Original quote: “TSMC is not pushing the most aggressive technology innovations, but they are optimizing and focusing on what they can actually ship. Focusing on yield, cost, and scale.”
Claude is the most powerful AI tool for no-code app building — Opinion (50/100)
At 7:22
Hype king crown goes to Claude? Subjective flex 💁♂️
Why this score: Opinion on Claude's superiority.
- Claude excels in reasoning/coding per updates (Claude 4.6 Sonnet), but 'most powerful' is debatable vs. GPT-4o or Gemini.
- No-code claims align with artifacts feature, but not uniquely 'most powerful'.
Original quote: “have you noticed how Claude is suddenly everywhere? It is indeed the most powerful tool right now which enabled many people to go from idea to app to launch without a single line of code.”
Intel's D1X in Hillsboro is their most advanced development site — Verified (85/100)
At 8:30
👌
Why this score: Confirmed accurate.
- D1X in Hillsboro, Oregon is Intel's key advanced R&D fab for process tech.
- Web context verifies it's the first with High-NA EUV tools.
Original quote: “Now, we leave Taiwan and cross the Pacific. We land in Hillsboro, Oregon, just outside Portland, inside Intel's most advanced development site, D1X.”
TSMC hesitates on High-NA EUV; Intel installed it for 18A process — Solid (80/100)
At 9:12
✅
Why this score: Spot on comparison.
- Intel integrated High-NA EUV into 18A dev; TSMC sticking to low-NA multi-patterning through 2029 due to cost/complexity.
- Matches web context on adoption strategies.
Original quote: “While TSMC hesitates on High-NA EUV adaption, Intel has already installed it and it's a part of the real process development for 18A and what comes next.”
High-NA EUV enables smaller features but slower, costlier, harder to control — Solid (75/100)
At 9:49
👌
Why this score: Precisely describes High-NA challenges.
- Tighter focus for smaller transistors confirmed; drawbacks like slower speed, sensitivity, complex recipes match industry reports.
- ASML notes HVM ramp in 2027-28.
Original quote: “High-NA EUV machine allows to focus light more tightly enabling smaller transistor features. That's the promise. But the cost is hidden in the details. These machines run slower and everything becomes more sensitive. More steps can fail. the manufacturing recipe overall becomes harder to control.”
High-NA EUV works but scaling to volume at low cost is the challenge — Opinion (50/100)
At 10:25
Fair take — the real hurdle is yield at scale ⚖️
Why this score: Reasonable assessment of industry bottleneck.
- High-NA proven in labs; scaling to HVM (thousands of wafers/day) and cost viability is the open question per ASML/Intel.
- Aligns with web context on 2027-28 ramp.
Original quote: “So the real question is not whether High-NA EUV works. It works but the question is whether they can figure out the recipe to make it to work at scale across thousands of wafers every day at a cost customer can accept.”
PowerVia harder to manufacture due to dual-side processing — Opinion (50/100)
At 10:30
Fair take — complexity is real but Intel shipped it 😤
Why this score: Subjective assessment of manufacturing difficulty.
- PowerVia adds wafer processing complexity for alignment, but Intel leads in commercialization (18A HVM 2026).
- Opinion on 'harder in reality' aligns with industry challenges, no contradiction.
Original quote: “[11:41] Signals will stay on the front, but power will come from the back. This is PowerVia technology. [11:47] It's cleaner in theory but much harder in reality because now suddenly you're processing both sides [11:54] of the wafer with perfect alignment and the process complexity explodes and…”
Panther Lake chips on 18A started shipping early 2026 — Verified (90/100)
At 12:32
✅
Why this score: Confirmed by current reports.
- Panther Lake (Core Ultra Series 3) launched Jan 2026 at CES, shipping in 200+ laptops on 18A process.
- Intel's 18A on track for HVM in 2H 2026 with yields >60%.
Original quote: “In early 2026, the first Panther Lake chips on 18A process started shipping.”
TSMC unbeatable on execution — Opinion (50/100)
At 13:21
Hype level: expert 💯 — but unbeatable? TSMC delays happen too 👀
Why this score: Subjective praise for TSMC's execution, not a hard fact.
- TSMC leads in advanced nodes (e.g., 2nm 2025), but faces fab delays in AZ, Germany, Japan due to costs/geopolitics.
- Widely respected, but 'unbeatable' is opinion amid Intel's 18A gains.
Original quote: “And this is where THMC excels. So far they've been unbeatable on execution.”
Terafab project tied to Tesla, SpaceX, xAI — Solid (80/100)
At 14:21
👌
Why this score: Terafab is real and matches description.
- Announced March 21, 2026 by Elon Musk; joint Tesla, xAI, Intel for 1+ terawatt AI compute.
- Vertically integrated fab covering design to packaging; minor note: xAI separate from SpaceX but Musk-linked.
Original quote: “Terafab, a project tied to Tesla, SpaceX, and xAI.”
xAI/Terafab aims for output of 25 advanced fabs in one integrated system — Solid (80/100)
At 14:30
👌
Why this score: Matches Terafab project details.
- Web context confirms Terafab as xAI/Tesla/SpaceX initiative for integrated chip production (logic, memory, packaging, testing).
- Ambitious scale aligns with reports of massive output goals, though exact '25 fabs' equivalence not quantified—still credible description.
Original quote: “and xAI. And the ambition is extreme. Not just a giant chip factory, but something that could reach the output of 25 advanced fabs all in one fully integrated system, logic, memory, packaging, and testing.”
Intel provides experience; Terafab provides scale and innovation — Solid (75/100)
At 15:12
Checks out ✓
Why this score: Accurate partnership dynamic.
- Intel contributes established manufacturing expertise (e.g., 14A process).
- Terafab's integrated 'one system' approach aligns with project goals for scale via massive investments.
Original quote: “Intel brings decades of experience in advanced chip manufacturing and advanced packaging. Terafab brings scale and a willingness to rethink the entire factory as one system.”
TSMC advanced nodes sold out for years ahead — Solid (85/100)
At 16:25
👌
Why this score: Confirmed by TSMC's Q1 2026 data.
- Advanced nodes (7nm+) are 74% of revenue; 2nm wafers through 2026 sold out to NVIDIA, Apple, etc.
- 'Many years' is reasonable given expansion plans.
Original quote: “TSMC's advanced node capacity is sold out for many years in advance, and companies like NVIDIA can't just rely on a single supply line forever.”
TSMC scales systems beyond transistors; Intel pushes transistor physics limits — Solid (85/100)
At 16:36
👌✅
Why this score: Accurate depiction of strategies.
- TSMC emphasizes system-level scaling and advanced packaging like CoWoS, not just transistors (web context confirms N2 node, A16 roadmap).
- Intel focuses on transistor physics with 18A node, RibbonFET GAA, and PowerVia (matches Intel's manufacturing comeback details).
Original quote: “TSMC says the transistor is no longer the main lever and they do amazing research on the device level, but at the same time they scale the system around it. While Intel is still pushing the limits of transistor physics, trying to squeeze more out of silicon. They have the same ambition but built on…”
Key metric now: most compute at lowest cost at scale, like AI cost per token — Opinion (50/100)
At 17:03
Shifting goalposts to what matters — execution over raw node size 😤
Why this score: Industry analysis aligns with opinion.
- Web context confirms focus on lowest cost compute at scale for AI, beyond transistor size.
- Analogy to AI cost per token fits current demands, though subjective metric.
Original quote: “So the question is no longer who has the most advanced transistor technology, who has the smallest transistor, but who can deliver the most compute at the lowest cost at scale. That's the metric. Now, just like in AI workloads, who gets the lowest cost per token?”
TSMC executes flawlessly; Intel may lead tech but execution key — Opinion (50/100)
At 17:16
Execution > tech — TSMC's rep precedes it ⚠️
Why this score: Subjective assessment backed by reputation.
- TSMC's execution noted in web context via high yields (98% on CoWoS) and rapid scaling.
- Intel's tech push real (18A success), but opinion on 'DNA' unverifiable; industry agrees execution critical.
Original quote: “Eventually, Intel might pull ahead on technology, but TSMC has execution in its DNA. And in this industry, being right is not enough. You have to be right and you have to execute flawlessly.”
See the full analysis with timestamps →